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Jitter and Spur Minimization in Fractional-N Digital Frequency Synthesizers: Modeling, Simulation, Analysis, and Design Methodologies - Analog Circuits and Signal Processing Xu Wang
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Jitter and Spur Minimization in Fractional-N Digital Frequency Synthesizers: Modeling, Simulation, Analysis, and Design Methodologies - Analog Circuits and Signal Processing
Xu Wang
This book presents a rigorous and practically grounded treatment of jitter and spur minimization in fractional-N digital phase locked loops (DPLLs), addressing one of the most critical challenges in modern frequency synthesis.
| Media | Books Hardcover Book (Book with hard spine and cover) |
| To be released | July 26, 2026 |
| ISBN13 | 9783032271853 |
| Publishers | Springer Nature Switzerland AG |
| Pages | 246 |
| Dimensions | 150 × 220 × 20 mm · 525 g (Weight (estimated)) |
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